Intel’s Live Demo of Larrabee at SC09

At the recent Supercomputing2009 Conference in Portland, OR, Intel’s Justin Rattner talked about the Rise of the 3D Internet as a tool for collaboration and presentation of HPC resources in a friendly way to users.  Disguised in the middle of his talk was a few slides about the upcoming Larrabee chipset with a live on-stage demo. He showed the chipset and ran a few demo’s with some help from Pradeep Dubey, and from my notes:

• SGEMM – Using only half the cores of larrabee, 380GFlops.  With all cores enabled:700Gflops
• SPMVM Sparse Matrices – QCD – FEM_CANT – About 8GFlops

In addition, he discusses the “MYO” (Mine-Yours-Ours) memory architecture where there is not the usual separation between CPU Memory & GPU Memory.  Another interesting tidbit was that not once during the entire hour-plus presentation did he refer to Larrabee as a Graphics Chip or GPU, but rather as a Compute Accelerator.  An interesting change in terminology for a company that previously wanted to wipe out NVidia in the graphics space.

The entire talk is now available on Youtube, and I’ve embedded it after the break.

This story written by Randall Hand

Randall Hand is a visualization scientist working for a federal research lab, aiding researchers to discover the insights buried within their terabyte datasets generated on some of the most powerful supercomputers in the world. He also runs VizWorld.com .